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k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d this is a family of 1,048,576 x 16 bit extended data out cmos drams. extended data out mode offers high speed random access of memory cells within the same row, so called hyper page mode. power supply voltage (+5.0v or +3.3v), refresh cycle (1k ref. or 4k ref.), access time (-45, -5 0 or -6 0 ), power consumption(normal or low power) and package type(soj or tsop-ii) are optional features of this family. all of this family have cas -before- ras refresh, ras -only refresh and hidden refresh capabilities. furthermore, self- refresh operation is available in l-version. this 1mx16 edo mode dram family is fabricated using samsung s advanced cmos pro- cess to realize high band-width, low power consumption and high reliability. it may be used as graphic memory unit for microcomp uter, personal computer and portable machines. ? part identification - k 4e171611d-j(t) (5v, 4k ref.) - k 4e151611d-j(t) (5v, 1k ref.) - k 4e171612d-j(t) (3.3v, 4k ref.) - k 4e151612d-j(t) (3.3v, 1k ref.) ? extended data out mode operation (fast page mode with extended data out) ? 2 cas byte/word read/write operation ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? self-refresh capability (l-ver only) ? ttl(5v)/lvttl(3.3v) compatible inputs and outputs ? early write or output enable controlled write ? jedec standard pinout ? available in plastic soj 400mil and tsop(ii) packages ? single +5v 10% power supply (5v product) ? single +3.3v 0.3v power supply (3.3v product) control clocks vbb generator refresh timer refresh control refresh counter row address buffer col. address buffer row decoder column decoder lower data out buffer ras ucas lcas w vcc vss dq0 to dq7 a0-a11 (a0 - a9) *1 a0 - a7 (a0 - a9) *1 memory array 1,048,576 x16 cells samsung electronics co., ltd. reserves the right to change products and specifications without notice. 1m x 16bit cmos dynamic ram with extended data out description features functional block diagram ? refresh cycles part no. v cc refresh cycle refresh period nor- l-ver k4e171611d 5v 4k 64ms 128ms k4e171612d 3.3v k4e151611d 5v 1k 16ms k4e151612d 3.3v ? performance range speed t rac t cac t rc t hpc remark -45 45ns 13ns 69ns 16ns 5v/3.3v -5 0 50ns 15ns 84ns 20ns 5v/3.3v -6 0 60ns 17ns 104ns 25ns 5v/3.3v ? active power dissipation speed 3.3v 5v 4k 1k 4k 1k -45 360 540 550 825 -5 0 324 504 495 770 -6 0 288 468 440 715 unit : mw s e n s e a m p s & i / o upper data in buffer upper data out buffer lower data in buffer dq 8 to dq15 oe note) *1 : 1k refresh
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 n.c n.c n.c w ras *a11(n.c) *a10(n.c) a0 a1 a2 a3 v cc v ss dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 n.c n.c lcas ucas oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 pin configuration (top views) pin name pin function a0 - a11 address inputs (4k product) a0 - a9 address inputs (1k product) dq0 - 15 data in/out v ss ground ras row address strobe ucas upper column address strobe lcas lower column address strobe w read/write input oe data output enable v cc power(+5v) power(+3.3v) n.c no connection v cc dq0 dq1 dq2 dq3 v cc dq4 dq5 dq6 dq7 n.c n.c w ras *a11(n.c) *a10(n.c) a0 a1 a2 a3 v cc v ss dq15 dq14 dq13 dq12 v ss dq11 dq10 dq9 dq8 n.c lcas ucas oe a9 a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 *a10 and a11 are n.c for k 4e151611(2)d (5v/3.3v, 1k ref. product) j : 400mil 42 soj t : 400mil 50(44) tsop ii ? k 4e17(5)1611(2)d-j ? k4e17(5)1611(2)d-t
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d absolute maximum ratings * permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol rating units 3.3v 5v voltage on any pin relative to v ss v in, v out -0.5 to +4.6 -1.0 to +7.0 v voltage on v cc supply relative to v ss v cc -0.5 to +4.6 -1.0 to +7.0 v storage temperature tstg -55 to +150 -55 to +150 c power dissipation p d 1 1 w short circuit output current i os address 50 50 ma recommended operating conditions (voltage referenced to vss, t a = 0 to 70 c) *1 : v cc +1.3v/15ns(3.3v), v cc +2.0v/20ns(5v), pulse width is measured at v cc *2 : -1.3v/15ns(3.3v), -2.0v/20ns(5v), pulse width is measured at v ss parameter symbol 3.3v 5v units min typ max min typ max supply voltage v cc 3.0 3.3 3.6 4.5 5.0 5.5 v ground v ss 0 0 0 0 0 0 v input high voltage v ih 2.0 - v cc +0.3 *1 2.4 - v cc +1.0 *1 v input low voltage v il -0.3 *2 - 0.8 -1.0 *2 - 0.8 v dc and operating characteristics (recommended operating conditions unless otherwise noted.) max parameter symbol min max units 3.3v input leakage current (any input 0 v in v in +0.3v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-2ma) v oh 2.4 - v output low voltage level(i ol =2ma) v ol - 0.4 v 5v input leakage current (any input 0 v in v in +0.5v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-5ma) v oh 2.4 - v output low voltage level(i ol =4.2ma) v ol - 0.4 v
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d *note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 , i cc3 and i cc6, address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one hyper page mode cycle time, t hpc . dc and operating characteristics (continued) i cc1 * : operating current ( ras and ucas , lcas , address cycling @t rc =min.) i cc2 : standby current ( ras = ucas = lcas = w =v ih ) i cc3 * : ras -only refresh current ( ucas = lcas =v ih , ras , address cycling @t rc =min.) i cc4 * : hyper page mode current ( ras =v il , ucas or lcas , address cycling @t hpc =min.) i cc5 : standby current ( ras = ucas = lcas = w =v cc -0.2v) i cc6 * : cas -before- ras refresh current ( ras , ucas or lcas cycling @t rc =min.) i cc7 : battery back-up current, average power supply current, battery back-up mode input high voltage(v ih )=v cc -0.2v, input low voltage(v il )=0.2v, ucas , lcas =0.2v, dq=don t care, t rc =31.25us(4k/l-ver), 125us(1k/l-ver) t ras =t ras min~300ns i ccs : self refresh current ras = ucas = lcas =v il , w = oe =a0 ~ a11=v cc -0.2v or 0.2v, dq0 ~ dq15=v cc -0.2v, 0.2v or open symbol power speed max units k 4e171612d k 4e151612d k 4e171611d k 4e151611d i cc1 don t care -45 -5 0 -6 0 100 90 80 150 140 130 100 90 80 150 140 130 ma ma ma i cc2 normal l don t care 1 1 1 1 2 1 2 1 ma ma i cc3 don t care -45 -5 0 -6 0 100 90 80 150 140 130 100 90 80 150 140 130 ma ma ma i cc4 don t care -45 -5 0 -6 0 110 100 90 110 100 90 110 100 90 110 100 90 ma ma ma i cc5 normal l don t care 0.5 200 0.5 200 1 200 1 200 ma ua i cc6 don t care -45 -5 0 -6 0 100 90 80 150 140 130 110 90 80 150 140 130 ma ma ma i cc7 l don t care 300 200 350 250 ua i ccs l don t care 150 150 200 200 ua
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d capacitance (t a =25 c, v cc =5v or 3.3v, f=1mhz) parameter symbol min max units input capacitance [a0 ~ a11] c in1 - 5 pf input capacitance [ ras , ucas , lcas , w , oe ] c in2 - 7 pf output capacitance [dq0 - dq15] c dq - 7 pf test condition (5v device) : v cc =5.0v 10%, vih/vil=2.4/0.8v, voh/vol=2.0/0.8v parameter symbol -45 -5 0 -6 0 units notes min max min max min max random read or write cycle time t rc 79 84 104 ns read-modify-write cycle time t rwc 105 115 140 ns access time from ras t rac 45 50 60 ns 3,4,10 access time from cas t cac 14 15 17 ns 3,4,5 access time from column address t aa 23/*20 25 30 ns 3,10 cas to output in low-z t clz 3 3 3 ns 3 output buffer turn-off delay from cas t cez 3 13 3 13 3 15 ns 6,19 oe to output in low-z t olz 3 3 3 ns 3 transition time (rise and fall) t t 2 50 2 50 2 50 ns 2 ras precharge time t rp 30 30 40 ns ras pulse width t ras 45 10k 50 10k 60 10k ns ras hold time t rsh 13 13 17 ns cas hold time t csh 36 40 50 ns cas pulse width t cas 7 / *6.5 10k 8 10k 10 10k ns 18 ras to cas delay time t rcd 19 31 20 35 20 43 ns 4 ras to column address delay time t rad 14 22 15 25 15 30 ns 10 cas to ras precharge time t crp 5 5 5 ns row address set-up time t asr 0 0 0 ns row address hold time t rah 9 10 10 ns column address set-up time t asc 0 0 0 ns 11 column address hold time t cah 7 8 10 ns 11 column address to ras lead time t ral 23 25 30 ns read command set-up time t rcs 0 0 0 ns read command hold time referenced to cas t rch 0 0 0 ns 8 read command hold time referenced to ras t rrh 0 0 0 ns 8 write command hold time t wch 8 10 10 ns write command pulse width t wp 8 10 10 ns write command to ras lead time t rwl 10 13 15 ns write command to cas lead time t cwl 7 8 10 ns 14 ac characteristics (0 c t a 70 c, see note 1,2) test condition (3.3v device) : v cc =3.3v 0.3v, vih/vil=2.2/0.7v, voh/vol=2.0/0.8v * k4e151611d-tc(l)45 (5v, 1k refresh) only
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d ac characteristics (continued) * k4e151611d-tc45 (5v, 1k refresh) only parameter symbol -45 -5 0 -6 0 units notes min max min max min max data set-up time t ds 0 0 0 ns 9,17 data hold time t dh 7 8 10 ns 9,17 refresh period (1k, normal) t ref 16 16 16 ms refresh period (4k, normal) t ref 64 64 64 ms refresh period (l-ver) t ref 128 128 128 ms write command set-up time t wcs 0 0 0 ns 7 cas to w delay time t cwd 28 32 36 ns 7,13 ras to w delay time t rwd 59 67 79 ns 7 column address w delay time t awd 37 42 49 ns 7 cas precharge to w delay time t cpwd 39 47 54 ns 7 cas set-up time ( cas -before- ras refresh) t csr 5 5 5 ns 15 cas hold time ( cas -before- ras refresh) t chr 10 10 10 ns 16 ras to cas precharge time t rpc 5 5 5 ns access time from cas precharge t cpa 25 28 35 ns 3 hyper page mode cycle time t hpc 18 20 25 ns 18 hyper page read-modify-write cycle time t hprwc 39 47 56 ns 18 cas precharge time (hyper page cycle) t cp 7 / * 6. 5 8 10 ns 12 ras pulse width (hyper page cycle) t rasp 45 200k 50 200k 60 200k ns ras hold time from cas precharge t rhcp 27 30 35 ns oe access time t oea 13 13 15 ns 3 oe to data delay t oed 10 13 15 ns output buffer turn off delay time from oe t oez 3 13 3 13 3 15 ns 6 oe command hold time t oeh 10 13 15 ns output data hold time t doh 4 5 5 ns output buffer turn off delay from ras t rez 3 13 3 13 3 15 ns 6,19 output buffer turn off delay from w t wez 3 13 3 13 3 15 ns 6 w to data delay t wed 15 15 15 ns oe to cas hold time t och 5 5 5 ns cas hold time to oe t cho 5 5 5 ns oe precharge time t oep 5 5 5 ns w pulse width (hyper page cycle) t wpe 5 5 5 ns ras pulse width ( c -b- r self refresh) t rass 100 100 100 us 20,21,22 ras precharge time ( c -b- r self refresh) t rps 79 90 110 ns 20,21,22 cas hold time ( c -b- r self refresh) t chs -50 -50 -50 ns 20,21,22
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d notes an initial pause of 200us is required after power-up followed by any 8 ras -only refresh or cas -before- ras refresh cycles before proper device operation is achieved. input voltage levels are vih/vil. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 2ns for all inputs. measured with a load equivalent to 2 ttl(5v)/1ttl(3.3v) loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs , t rwd , t cwd , t awd and t cpwd are non restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min), then the cycle is a read- modify-write cycle and the data output will contain the data read from the selected address. if neither of the above conditions is satisfied, the condition of the data out is indeterminate. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to cas falling edge in early write cycles and to w falling edge in oe controlled write cycle and read-modify-write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . k4 e17(5) 16 11 (2) d truth table ras lcas ucas w oe dq0 - dq7 dq8-dq15 state h x x x x hi-z hi-z standby l h h x x hi-z hi-z refresh l l h h l dq-out hi-z byte read l h l h l hi-z dq-out byte read l l l h l dq-out dq-out word read l l h l h dq-in - byte write l h l l h - dq-in byte write l l l l h dq-in dq-in word write l l l h h hi-z hi-z - 8. 6. 5. 10. 9. 3. 2. 1. 4. 7.
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t asc , t cah are referenced to the earlier cas falling edge. t cp is specified from the later cas rising edge in the previous cycle to the earlier cas falling edge in the next cycle. t cwd is referenced to the later cas falling edge at word read-modify-write cycle. t cwl is specified from w falling edge to the earlier cas rising edge. t csr is referenced to the earlier cas falling edge before ras transition low. t chr is referenced to the later cas rising edge after ras transition low. t csr t chr ras lcas ucas 22. 13. 19. 12. 11. t ds, t dh is independently specified for lower byte dq(0-7), upper byte dq(8-15) t asc 3 6ns, assume t t =2.0ns. if ras goes to high before cas high going, the open circuit condition of the output is achieved by cas high going. if cas goes to high before ras high going, the open circuit condition of the output is achieved by ras high going. if t rass 3 100us, then ras precharge time must use t rps instead of t rp . for ras -only refresh and burst cas -before- ras refresh mode, 4096(4k)/1024(1k) cycles of burst refresh must be executed within 64ms/16ms before and after self refresh, in order to meet refresh specification. for distributed cas -before- ras with 15.6us interval, cas -before- ras refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. 18. 16. 15. 14. 21. 20. 17.
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t crp ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq7 column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t asr t rah t asc t cah t crp t aa t oea t cac t clz t rac open t cez t rch don t care undefined lcas v ih - v il - t crp t csh t rsh t rcd t cas t rad t rrh v oh - v ol - dq8 ~ dq15 t cac t clz t rac open data-out data-out t cez t oez t oez t rcs word read cycle t olz
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d note : d in = open lower byte read cycle ras v ih - v il - lcas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq7 column address row address t ras t rc t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t aa t oea t cac t clz t rac open data-out t oez t cez t rrh t rch don t care undefined t crp t rpc ucas v ih - v il - open v oh - v ol - dq8 ~ dq15 t rcs t olz
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d note : d in = open upper byte read cycle ras v ih - v il - lcas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - dq0 ~ dq7 column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t aa t oea t cac t clz t rac open data-out t oez t cez t rrh t rch don t care undefined ucas v ih - v il - open v oh - v ol - dq8 ~ dq15 t crp t rpc t rcs t olz
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp don t care word write cycle ( early write ) note : d out = open undefined lcas v ih - v il - t wcs v ih - v il - dq0 ~ dq7 t ds v ih - v il - dq8 ~ dq15 t crp t csh t rsh t rcd t cas t crp t wch t wp t dh data-in t ds t dh data-in
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t crp ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row address t ras t rc t rp t ral t rad t asr t rah t asc t cah don t care lower byte write cycle ( early write ) note : d out = open undefined lcas v ih - v il - t wcs v ih - v il - dq0 ~ dq7 t ds v ih - v il - dq8 ~ dq15 t crp t csh t rsh t rcd t cas t wch t wp t dh data-in t crp
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp don t care upper byte write cycle ( early write ) note : d out = open undefined lcas v ih - v il - t wcs v ih - v il - dq0 ~ dq7 v ih - v il - dq8 ~ dq15 t wch t wp t ds t dh data-in t crp
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t crp don t care word write cycle ( oe controlled write ) note : d out = open undefined lcas v ih - v il - v ih - v il - dq0 ~ dq7 v ih - v il - dq8 ~ dq15 t crp t rsh t rcd t cas t crp t rwl t wp t cwl t dh t dh data-in column address t oeh t oed t ds t ds data-in t csh t cah
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row address t ras t rc t rp t ral t rad t asr t rah t asc t cah don t care lower byte write cycle ( oe controlled write ) note : d out = open undefined lcas v ih - v il - t rwl v ih - v il - dq0 ~ dq7 t ds v ih - v il - dq8 ~ dq15 t crp t csh t rsh t rcd t cas t crp t wp t cwl t dh data-in t crp t rpc t oeh t oed
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp don t care upper byte write cycle ( oe controlled write ) note : d out = open undefined lcas v ih - v il - v ih - v il - v ih - v il - t crp t rwl t wp t cwl t ds t dh data-in t oeh t oed dq0 ~ dq7 dq8 ~ dq15 t crp
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t rwl ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr. t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp don t care word read - modify - write cycle undefined lcas v ih - v il - v i/oh - v i/ol - dq0 ~ dq7 v i/oh - v i/ol - dq8 ~ dq15 t wp t cwl t ds t dh t rsh t rcd t cas t crp t awd t cwd t oea t rwd t oed t oez t rac t aa t oez t rac t aa t ds t oed t dh valid data-out valid data-in valid data-out valid data-in t cac t clz t cac t clz t olz t olz
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t rwl ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr. t ras t rwc t rp t csh t rad t asr t rah t asc t cah t crp don t care lower-byte read - modify - write cycle undefined lcas v ih - v il - v i/oh - v i/ol - dq0 ~ dq7 v oh - v ol - dq8 ~ dq15 t wp t cwl t ds t dh t rsh t rcd t cas t crp t awd t cwd t oea t rwd t oed t oez t rac t aa valid data-out valid data-in t rpc t cac t clz open t olz
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t rwl ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp don t care upper-byte read - modify - write cycle undefined lcas v ih - v il - v oh - v ol - dq0 ~ dq7 v i/oh - v i/ol - dq8 ~ dq15 t wp t cwl t awd t cwd t oea t rwd t oez t rac t aa t ds t oed t dh valid data-out valid data-in t crp t rpc t cac t clz open t olz
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t asc t olz t clz t olz t clz ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp t rcd t crp don t care hyper page mode word read cycle undefined lcas v ih - v il - v oh - v ol - dq0 ~ dq7 v oh - v ol - dq8 ~ dq15 column address t cas t cas t cas t cas t cp t cp t cp t rez t hpc t hpc t hpc t rhcp t csh t rcd t crp t cas t cas t cas t cas t cp t cp t cp t rad t rcs t oea t rch t rrh column address column addr t oez t oep t cho t aa t cpa t aa t cac valid data-out t oep t oez t rac t cac t doh valid data-out valid data-out t och t cpa t aa t cac t cac t cpa t oez valid data-out valid data-out valid data-out t oep t oez t rac t cac valid data-out valid data-out t oez valid data-out valid data-out t doh t oea t asr t rah t asc t cah t asc t cah t cah t cah t asc t ral
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t oea t olz t clz ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp t crp don t care hyper page mode lower byte read cycle undefined lcas v ih - v il - v oh - v ol - dq0 ~ dq7 v oh - v ol - dq8 ~ dq15 column address t rez t rhcp t csh t rcd t cas t cas t cas t cas t cp t cp t cp t rad t rcs t rch t rrh column address column addr t oez t oep t cho t cpa t cac valid data-out t oep t oez t rac t cac t doh valid data-out valid data-out t och t cpa t cac t cac t cpa t oez valid data-out valid data-out open ? t rpc t asr t rah t asc t cah t asc t cah t cah t asc t cah t asc t aa t hpc t hpc t hpc t aa t aa t aa t oea t ral
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr. t rasp t rp t rcd t asr t crp don t care hyper page mode upper byte read cycle undefined lcas v ih - v il - v oh - v ol - dq0 ~ dq7 v oh - v ol - dq8 ~ dq15 column address t cas t cas t cas t cas t cp t cp t cp t rez t hpc t hpc t hpc t rhcp t csh t crp t rah t asc t cah t cah t cah t asc t cah t rcs t oea t rch t rrh column address column addr. t oez t oep t cho t cpa t cac valid data-out t oep t oez t rac t cac t olz t clz t doh valid data-out valid data-out t och t cpa t cac t cac t cpa t oez valid data-out valid data-out open ? t asc t rpc t rpc t rad t asc t aa t aa t aa t oea t ral
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp t rcd t asr t crp don t care hyper page mode word write cycle ( early write ) undefined lcas v ih - v il - v ih - v il - dq0 ~ dq7 v ih - v il - dq8 ~ dq15 t crp t hpc t rhcp t rad t rah t cah t cah t asc t cah t asc valid data-in t ds ? column address column address t cas t cp t cas t cp t cas t rsh ? t rcd t crp t hpc t hpc t cas t cp t cas t cp t cas t rsh ? t csh t asc ? ? t wp t wcs t wch t wp t wcs t wch t wp t wcs t wch ? ? ? valid data-in valid data-in ? ? t dh t ds t dh t ds t dh valid data-in valid data-in valid data-in ? ? t dh t dh t dh t ds t ds t ds note : d out = open t hpc t ral
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp t asr t crp don t care hyper page mode lower byte write cycle ( early write ) undefined lcas v ih - v il - v ih - v il - dq0 ~ dq7 v ih - v il - dq8 ~ dq15 t rpc t rhcp t rad t rah t cah t cah t asc t cah t asc valid data-in t ds ? column address column address t rcd t crp t hpc t hpc t cas t cp t cas t cp t cas t rsh ? t csh t asc ? ? t wp t wcs t wch t wp t wcs t wch t wp t wcs t wch ? ? ? valid data-in valid data-in ? ? t dh t ds t dh t ds t dh note : d out = open t ral
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t wcs ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp t asr t crp don t care hyper page mode upper byte write cycle ( early write ) undefined lcas v ih - v il - v ih - v il - dq0 ~ dq7 v ih - v il - dq8 ~ dq15 t rpc t rhcp t rad t rah t cah t cah t asc t cah t asc valid data-in t ds ? column address column address t rcd t crp t hpc t hpc t cas t cp t cas t cp t cas t rsh ? t csh t asc ? ? t wp t wch t wp t wcs t wch t wp t wcs t wch ? ? ? valid data-in valid data-in ? ? t dh t ds t dh t ds t dh note : d out = open ? ? t ral
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq7 row addr t csh t rasp t rp t asr don t care hyper page mode word read - modify - write cycle undefined t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t asc t cah t ral t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t aa t rac t oea t clz t cac t oez t cpwd t oed t asc t clz t oea t cac t aa t dh t oed lcas v ih - v il - t rcd t cp t cas t cas t crp t crp t crp v i/oh - v i/ol - dq8 ~ dq15 valid data-out t dh t aa t rac t clz t cac valid data-in valid data-out valid data-in t clz t cac t aa t dh t oez t oed t ds t ds t ds t oed t oez t oez valid data-out valid data-in valid data-out valid data-in t ds t hprwc t rsh t rwl t rcs t rah
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t asc ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq7 row addr t csh t rasp t rp t asr don t care hyper page mode lower byte read - modify - write cycle undefined t rad t cah t wp t dh col. addr col. addr t asc t cah t ral t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t aa t rac t oea t clz t cac t oez t cpwd t oed t clz t oea t cac t aa t dh t oed t rwl t rcd t cp t cas t cas t crp t crp t crp v i/oh - v i/ol - dq8 ~ dq15 t ds t oez valid data-out valid data-in valid data-out valid data-in t ds t rpc t rsh open lcas v ih - v il - ucas v ih - v il - t hprwc t rcs t olz t olz t rah
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t asc t crp ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq7 row addr t csh t rasp t rp t asr don t care hyper page mode upper byte read - modify - write cycle undefined t rad t cah t wp t dh col. addr col. addr t cah t ral t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t aa t rac t oea t clz t cac t oez t cpwd t oed t clz t oea t cac t aa t dh t oed t rwl t rcd t cp t cas t cas t crp t crp v i/oh - v i/ol - dq8 ~ dq15 t ds t oez valid data-out valid data-in valid data-out valid data-in t ds t rpc t rsh open lcas v ih - v il - ucas v ih - v il - t hprwc t asc t rcs t rah t olz t olz
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d hyper page read and write mixed cycle ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp don t care undefined v i/oh - v i/ol - dq0 ~ dq7 t wez t cp t hpc t hpc t hpc t rcd t rah t asc t cah t cah t cah t asc t cah t rch t rcs t rcs t rch t asc column address col. addr valid data-out t rez t aa t wcs valid data-out valid data-out valid data-in t rac col. addr t cas t asr t cas t cas t cas t asc t cp t rch t wch t wpe t clz t cpa t wed t aa t wez t ds t dh t cac t oea t cp t hpc t hpc t cas t cas t cas t cas t cp v i/oh - v i/ol - dq8 ~ dq15 t wez valid data-out t rez t aa valid data-out valid data-out valid data-in t rac t aa t wez t ds t dh t cac t oea lcas v ih - v il - ucas v ih - v il - t cp t hpc t cp read( t cac ) read( t cpa ) write read( t aa ) t rad t rhcp t ral
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t crp open ras v ih - v il - ucas v ih - v il - a v ih - v il - row addr t rc t rp t asr t crp ras - only refresh cycle lcas v ih - v il - t ras t rah note : w , oe , d in = don t care d out = open t rpc cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - ucas v ih - v il - t rc t rp lcas v ih - v il - t ras t rpc t cp t rpc t csr t chr t cp t csr t chr t cez open v oh - v ol - dq0 ~ dq7 v oh - v ol - dq8 ~ dq15 don t care t rp undefined
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t oez data-in data-out t rp ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t chr t rcd t rsh t rad t asr t rah t asc t crp don t care hidden refresh cycle ( read ) undefined lcas v ih - v il - v oh - v ol - dq0 ~ dq7 v oh - v ol - dq8 ~ dq15 t rsh t rcd t crp t wrh column address t oea t ras t rc t chr t cah t rcs t aa t rac t clz t cac data-out t cez open open t rp t rez t wez t olz t ral
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d t wcs t rp ras v ih - v il - ucas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t chr t rcd t rsh t rad t asr t rah t asc t crp don t care hidden refresh cycle ( write ) undefined lcas v ih - v il - v ih - v il - dq0 ~ dq7 v ih - v il - dq8 ~ dq15 t rsh t rcd t crp t wrh column address t ras t rc t chr t cah t wrp t ds note : d out = open t wp t wch data-in t dh t ds data-in t dh t rp
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d open cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - ucas v ih - v il - t rps lcas v ih - v il - t rass t rpc t cp t rpc t csr t cez open v oh - v ol - dq0 ~ dq7 v oh - v ol - dq8 ~ dq15 t wrp t wrh w v ih - v il - t chs t cp t csr t chs test mode in cycle note : oe , a = don t care ras v ih - v il - ucas v ih - v il - t rp lcas v ih - v il - t rc t rpc t cp t rpc t csr open v oh - v ol - dq0 ~ dq15 t chr t cp t csr t chr t rp t rp don t care undefined t wts t wth w v ih - v il - t cez t ras
k4e171611d, k4e151611d cmos dram k4e171612d, k4e151612d 42 soj 400mil 0 . 4 0 0 ( 1 0 . 1 6 ) 0 . 4 3 5 ( 1 1 . 0 6 ) 0 . 4 4 5 ( 1 1 . 3 0 ) 1.080 (27.43) 1.070 (27.19) max 1.091 (27.71) m a x 0 . 1 4 8 ( 3 . 7 6 ) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.015 (0.38) 0.027 (0.69) 0.012 (0.30) 0.006 (0.15) 0 . 3 6 0 ( 9 . 1 5 ) 0 . 3 8 0 ( 9 . 6 5 ) min #42 #1 0.0375 (0.95) 0.050 (1.27) units : inches (millimeters) 50(44) tsop(ii) 400mil units : inches (millimeters) max 0.047 (1.20) min 0.002 (0.05) 0.018 (0.45) 0.010 (0.25) 0.0315 (0.80) 0.034 (0.875) 0.821 (20.85) 0.829 (21.05) 0.841 (21.35) max 0.010 (0.25) 0.004 (0.10) 0 . 4 0 0 ( 1 0 . 1 6 ) 0 . 4 7 1 ( 1 1 . 9 6 ) 0 . 4 5 5 ( 1 1 . 5 6 ) 0~8 0.030 (0.75) 0.018 (0.45) typ 0.010 (0.25) o package dimension

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